1. Technical Field of the Invention
The present invention relates to field programmable gate arrays (FPGAs), and, more particularly, to an interface block for use with such circuitry.
2. Description of Related Art
Referring to FIG. 1, there is shown a prior art bidirectional I/O device 100 that, takes an output OUT (not-OUT) and provides it to an output PAD 101. OUT and not-OUT are provided as inputs to a multiplexer 102, the output S01 of which is selected by the contents of memory elements 103 and 104. Similarly, OUT and not-OUT are provided as inputs to a multiplexer 105, the output of which is selected by the contents of memory elements 106 and 107 and provided to the input of a D-type register 108. The output of the D-type register 108 is fed in inverted and non-inverted form to the input of a multiplexer 109, the output S02 of which is selected by the contents of memory elements 110 and 111. An output buffer 112 selects one input at a time from S01 and S02 and provides the output to the pad 101.
At each positive edge of the clock (feeding the register 108), the presently selected data OUT signal from the core is made available at the PAD. The data rate of the PAD is therefore limited to the clock frequency. To avoid conflicts at the output, only one of memory elements 103, 104, 110 and 111 is held high at any given time.
When operating as an input, an input buffer 113 takes input from the PAD and delivers it to the core (IN). In this mode, the output buffer 112 operates in tristate mode (selected by signal TS), thereby presenting a high impedance to the PAD.
Power consumption within CMOS circuitry is proportional to the frequency of clock signals used within the circuitry. As the clock frequency increases, the die temperature also increases, which requires a correspondingly increasing amount of heat to be dissipated. As the devices have increased in speed, the limiting factor on clock frequency has become the amount of heat a given package can dissipate. Dual data rate (DDR) techniques have been used to enable a halving in clock rates for a given clock frequency. However, these tend to require a relatively high number of registers and in-line multiplexers, which adds undesirable complexity and consumes an undesirable amount of on-chip real-estate.